1149.1 std

(page 1)
Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined

(page 3 introduction)
This standard defines a test access port and boundary-scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits

History of the development of this standard
The process of developing this standard began in 1985, when the Joint European Test Action Group (JETAG) was formed in Europe

The major changes to this standard introduced by IEEE Std 1149.1a-1993 were
— The addition of two optional instructions, CLAMP and HIGHZ, which standardized the names and specifications of features often implemented as design-specific features
— The addition of an optional facility to switch a component from a mode in which it complies to this standard into one in which it supports another design-for-test approach

(page 4)
The principal changes introduced are
To reduce the risk of accidental entry into test mode
To increase the flexibility with which instructions may be implemented and merged,

To enable more efficient implementation of boundary-scan register cells provided at system logic outputs, the source of data to be captured in such cells in response to the SAMPLE instruction is now allowed to be at the connected system pin

To permit more flexible boundary-scan register cell implementations, sharing of circuitry between the boundary-scan register and other elements of the test and/or system logic has been allowed in limited cases

(page 9)
1. Overview
1.1 Scope

1.2 Purpose
1.2.1 An overview of the operation of IEEE Std 1149.1
The first steps would be, in general, to load serially into the component the instruction binary code for the particular operation to be performed.


(page 10)


Once the instruction has been loaded, the selected test circuitry is configured to respond.

After execution of the test instruction, based where necessary on supplied data, the results of the test can be examined by shifting data out of the component to or through the bus master.

1.2.2 The use of IEEE Std 1149.1 to test an assembled product
This subclause outlines the use of the boundary-scan circuitry defined by this standard during the process of testing an assembled product such as a printed circuit board.

This approach can be applied to a board constructed from integrated circuits, to a system constructed from printed circuit boards, or to a complex integrated circuit constructed from a set of simpler functional modules.

At the board level, goal a) and goal b) typically are achieved by using in-circuit test techniques; for goal c), a functional test is required.