std1450 STIL std

Abstract: Standard Test Interface Language (STIL) provides an interface between digital test generation tools and test equipment.

(page 3)
Introduction

Standard Test Interface Language (STIL) was initially developed by an ad-hoc consortium of test equipment vendors, computer-aided engineering (CAE) and computer-aided design (CAD) vendors, and integrated circuit (IC) manufacturers, to address the lack of a common solution for transferring digital test data from the generation environment to the test equipment.

The need for a common interchange format for large volumes of digital test data was identified as an overriding priority for the work; as such, the scope of the work was constrained to those aspects of the test environment that contribute significantly to the volume issue, or are necessary to support the comprehension of that data.

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1. Overview
Standard Test Interface Language (STIL) is a standard language that provides an interface between digital test generation tools and test equipment

STIL is a representation of information needed to define digital test operations in manufacturing tests. the overall STIL language is inherently more flexible than any particular tester.

Figure 2 shows how STIL fits into the data flow between computer-aided engineering (CAE)/simulation and the test environment.

Another issue presented in Figure 2 is the need for data from the tester to be transmitted back to the CAE/simulation environment for the purpose of correlating simulation data to tester data.

1149.7 std

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Abstract: This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001.

(page 6)
introduction

This standard defines a debug and Test Access Port that provides both compatibility with IEEE Std
1149.1TM-2001a and operation with as few as two pins.

The process of developing this standard began in 2004 when the Mobile Industry Processor Interface (MIPI) Alliance Test and Debug Working Group was formed. During 2004, a standard that addressed the needs of both test and debug was described and requirements were gathered.

Once the requirements gathering process was completed in 2004, the Test and Debug Working Group turned its attention to proposals for addressing the above requirements

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1. Overview
1.1 Scope
The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS).

1.2 Purpose
1.3 Contrasting IEEE Std 1149.1-2001 and this standard
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IEEE Std 1149.1-2001 was introduced to address issues related to the manufacturing test of boards and systems.

This standard is complementary to IEEE Std 1149.1-2001 and does not seek to replace it.

This standard differs from IEEE Std 1149.1-2001 as it intentionally blurs the boundary between boards, packages, and chips.

1149.4 std

Abstract:
The testability structure for digital circuits described in IEEE Std 1149.1-1990 has been extended to provide similar facilities for mixed-signal circuits

(page 3)
introduction

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1. Overview
1.1 Organization of the standard

1.2 Context

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In Figure 1, the component that is the subject of this standard is shown shaded. In a typical mixed-signal analog and digital PCA,

The PCA is tested, both in production (to verify correct manufacture) and in field service (to detect and locate faults), using automatic test equipment (ATE) to supply test signals to, and to collect test responses from, some or all of the component pins.

1.3 Scope of the standard
1.3.2 Interconnect testing
1.3.3 Parametric test
The second objective of this standard, parametric test, recognizes the fact that groups of one or more discrete components are often interposed between integrated circuits, performing functions such as level shifting, passive filtering, and ac coupling.

(p 10)
Also illustrated in Figure 3 is an example of differential interconnect, which is a pair of pathways carrying signals whose information content is defined by the pair of signals rather than by either one signal individually.

A similar situation from the testing point of view is illustrated in Figure 4, where an analog signal to be transmitted is passed through an analog-to-digital converter, transmitted as a parallel set of digital signals, and passed through a digital-to-analog converter to form a received analog signal.

1149.6 std

(page 1)

Abstract:
This standard augments IEEE Std 1149.1 to improve the ability for testing differential
and/or ac-coupled interconnections between integrated circuits on circuit boards and systems

(page 4)
(page 8)
1. Overview
1.1 Scope
This standard defines extensions to IEEE Std 1149.1 to standardize the Boundary-Scan structures and methods required to ensure simple, robust, and minimally intrusive Boundary-Scan testing of advanced digital networks.


1.2 Organization of the standard

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1.3 Context

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1.4 Objectives
The objective of this standard is to provide design guidance for testability circuitry added to an IC in addition to testability provisions specified by IEEE Std 1149.1, such that when such an IC contains differential signaling and/or is AC-coupled with other ICs compliant to this standard, board and system level tests can be readily and accurately conducted, with enhanced defect coverage

3. Definitions and acronyms
3.1 Definitions
3.1.1 AC-coupling
The use of series capacitance in a signal path.
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3.1.2 AC pins: Advanced I/O
pins that require a time-varying (AC) signal to permit testing of their interconnections.

3.1.3 AC test mode:
A test mode that enables Boundary-Scan testing between AC pins that are AC-coupled or DC-coupled.

3.1.4 AC Test Signal:
A signal generated by the AC test mode that is used to modulate static test data into a
time-varying signal that can pass through AC-coupling. A test receiver and detector is used to recover the static test data value from within the time-varying signal.

1149.1 std

(page 1)
Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined

(page 3 introduction)
This standard defines a test access port and boundary-scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits

History of the development of this standard
The process of developing this standard began in 1985, when the Joint European Test Action Group (JETAG) was formed in Europe

The major changes to this standard introduced by IEEE Std 1149.1a-1993 were
— The addition of two optional instructions, CLAMP and HIGHZ, which standardized the names and specifications of features often implemented as design-specific features
— The addition of an optional facility to switch a component from a mode in which it complies to this standard into one in which it supports another design-for-test approach

(page 4)
The principal changes introduced are
To reduce the risk of accidental entry into test mode
To increase the flexibility with which instructions may be implemented and merged,

To enable more efficient implementation of boundary-scan register cells provided at system logic outputs, the source of data to be captured in such cells in response to the SAMPLE instruction is now allowed to be at the connected system pin

To permit more flexible boundary-scan register cell implementations, sharing of circuitry between the boundary-scan register and other elements of the test and/or system logic has been allowed in limited cases

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1. Overview
1.1 Scope

1.2 Purpose
1.2.1 An overview of the operation of IEEE Std 1149.1
The first steps would be, in general, to load serially into the component the instruction binary code for the particular operation to be performed.


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Once the instruction has been loaded, the selected test circuitry is configured to respond.

After execution of the test instruction, based where necessary on supplied data, the results of the test can be examined by shifting data out of the component to or through the bus master.

1.2.2 The use of IEEE Std 1149.1 to test an assembled product
This subclause outlines the use of the boundary-scan circuitry defined by this standard during the process of testing an assembled product such as a printed circuit board.

This approach can be applied to a board constructed from integrated circuits, to a system constructed from printed circuit boards, or to a complex integrated circuit constructed from a set of simpler functional modules.

At the board level, goal a) and goal b) typically are achieved by using in-circuit test techniques; for goal c), a functional test is required.

1500 std

Introduction

(page 5)
IEEE Std 1500 is a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry.

Core test language (CTL) is the official mechanism for describing IEEE 1500 wrappers and test data associated with cores.

IEEE Std 1500 was broadly influenced by the past work of the IEEE Std 1149.1™ Working Group and has several members from that group.

Objective of the IEEE 1500 effort

The Embedded Core Test Working Group was approved in 1997 with the charter to develop a standard test method for integrated circuits (ICs) containing embedded cores, i.e., reusable megacells

(page 11)
1. Overview
IEEE Std 1500™ defines a scalable architecture for independent, modular test development and test application for embedded design blocks and also enables test of the external logic surrounding these cores

The IEEE 1500 architecture comprises hardware requirements, through the definition of a standardized core wrapper, and uses a test-specific language to communicate information between core providers and core users.

IEEE Std 1500 specifically focuses on defining test requirements for unidirectional non-tristate digital terminals, as these represent a minimum and mandatory set of requirements upon which the more complex bidirectional terminals are based.

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1.1 Scope
1.2 Purpose
2. Normative references

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3. Definitions, acronyms, and abbreviations
This clause lists some definitions of terms that have been used throughout this standard.

3.1 Definitions

3.1.1 access mechanisms: Mechanisms by which signals may be propagated to and from a core, from either embedded circuitry or from the primary inputs and outputs of the system chip.







3. Definitions, acronyms, and abbreviations
3.1 Definitions
4. Structure of this standard
5. Introduction and motivations of two compliance levels
6. Overview of the IEEE 1500 scalable hardware architecture
6.3 Wrapper instruction register (WIR)
7. WIR instructions
7.1 Introduction
Instructions loaded into the WIR, together with the IEEE 1500 wrapper signals, determine the mode of operation of the wrapper and possibly the core itself.

7.2 Response of the wrapper circuitry to instructions
(skip)

8. Wrapper serial port (WSP)
IEEE Std 1500 defines mandatory WSP terminals to control serial access to the WIR, the WBY, and the WBR.

WRSTN: When asserted, WRSTN puts the wrapper into its normal system mode. The signal may be used to reset other WRs or wrapper circuitry as needed.

CaptureWR, ShiftWR, UpdateWR: These terminals control and enable WR operations. When one of these signals is asserted to logic 1 and the other two signals are deasserted to logic 0, a corresponding Capture, Shift, or Update operation will be enabled for the selected WR. While the WIR or WBY is selected, the enabled operation occurs synchronously to WRCK.

dt09 lv Improved Core Isolation and Access for Hierarchical Embedded Test

So 1500 is essentially giving each core a standard interface.

"We selected a star configuration, as opposed to a daisy-chain one, for various reasons, from both a design and test perspective. In a star configuration, each core can be exercised and verified independently from other cores in the context of the entire circuit without having to modify the testbenches or vectors."
(So for daisy chain, our software needs to modify corresponding test benches)

8/20/10 Fri
Each core’s WSP is at the second level of the hierarchy, which is implemented according to IEEE Std 1500.

The serial input is shared by all test ports, but each test port has a dedicated enable (enTP1 to enTP5) and serial output (fromTP1 to fromTP5).

The extTM control signal makes the WBR accessible either as a single or multiple segments, at the core boundary so that it becomes part of the scan test of the next level up.
(Comments: "accessible" here is the keyword. By making these WBR accessible to the upper level, the core can be considered as a blackbox in a upper level scan test.)

Shared isolation is an improvement to IEEE Std1500 that can minimize the amount of test-dedicated circuitry required for core isolation and enable atspeed testing within and between cores